1. The Basic Triangle of CPU Performance: Clock Speed, IPC, and Core Count
To understand the performance difference between M5 and M4, first consider what CPU performance consists of. The classic formula is:
Performance ≈ clock speed × IPC × core count
Together, these three factors determine how much work a CPU can do. Let us examine them one by one.
1.1 Clock Speed / Clock Frequency
Clock speed is measured in GHz (gigahertz). It essentially describes how many times the CPU’s internal clock “ticks” per second. The M4 runs at 4.46 GHz, meaning 4.46 billion clock ticks per second; the M5 runs at 4.61 GHz, or 4.61 billion ticks per second.
Think of this as the speed of a factory conveyor belt. The faster the belt moves, the more workpieces can pass through in a given time. The crucial point, however, is that conveyor-belt speed is not the same as factory output. You must also know how many operations workers can complete on each cycle of the belt. This leads to IPC.
1.2 IPC (Instructions per Cycle)
IPC measures how many instructions a CPU can execute during each clock cycle. It directly reflects the quality of the chip’s microarchitecture.
Using the factory analogy again, clock speed is the belt speed, while IPC is how many operations workers can complete each time the belt makes a cycle. If the production line is improved—for example, a worker who could previously tighten only one screw at a time receives a better tool that can tighten two—output doubles even if belt speed remains unchanged.
The M5’s IPC is approximately 10% higher than the M4’s. At the same clock speed, it can therefore complete about 10% more work per cycle. Combined with the increase from 4.46 to 4.61 GHz, or roughly 3.4%, this produces an overall single-core improvement of about 15%.
The blogger’s claim that “clock speed is the factor that most directly affects the experience” might have been correct from the 1990s through the early 2000s, when Intel and AMD primarily improved performance by increasing frequency. Since around 2005, however, physical constraints in power consumption and cooling—the so-called “frequency wall”—have shifted the chip industry’s main optimization efforts toward higher IPC and multi-core scaling.
1.3 Multi-Core Scaling
Because single-core frequency is difficult to increase substantially, modern CPUs use multiple cores in one chip so that work can proceed in parallel. Multi-core performance is not simply “core count × single-core performance,” because cores must share data and coordinate tasks, which introduces communication overhead.
The M5’s multi-core performance is approximately 25% higher than the M4’s, substantially more than its 15% single-core improvement. This indicates that Apple improved not only each individual core but also the mechanisms by which cores share data, primarily through better cache and bus design.
2. The Cache Hierarchy: Why L2 Cache Matters
2.1 L2 Cache
To understand the value of cache, begin with a fundamental mismatch: the CPU computes much faster than memory can supply data.
Imagine that the CPU is an exceptionally skilled chef who can make 100 cuts per second, while the ingredients—the data—must be transported from a distant warehouse, the main DRAM. Each delivery takes several seconds. If the chef has to wait for a warehouse delivery before every cut, 90% of the chef’s time is spent waiting.
A cache is like a small refrigerator next to the kitchen or a cutting board on the counter. Its capacity is limited, but it is extremely close to the chef and can be accessed with almost no wait.
Modern CPUs usually have three cache levels:
L1 cache is the fastest, sits directly beside each CPU core, and has the smallest capacity—usually tens of KB—with latency of about one or two clock cycles. It is like the cutting board beside the chef, holding the most frequently used ingredients.
L2 cache is larger than L1 but slightly slower—usually hundreds of KB to several MB—with latency of about 10–20 cycles. It is like the small refrigerator beside the kitchen. The M4 has 20 MB of L2 cache in total, while the M5 increases this to 28 MB. This 40% capacity increase means more data can be kept close to the processor, reducing trips to main memory.
L3 cache, also called the last-level cache, is larger and slower and is shared by all cores, usually with a capacity of tens of MB.
For AI inference, model-weight matrices are very large. A larger cache can temporarily hold more model parameters close to the processor, reducing repeated reads from main memory and improving computation speed. This is why the analysis described the M5’s cache improvement as “Apple’s secret weapon.”
2.2 Front-End Bandwidth
A CPU’s workflow can be divided roughly into two stages. The front end fetches instructions from memory or cache and decodes them; the back end actually executes those instructions.
Think of the front end as a restaurant order taker and the back end as the kitchen. If the order taker can accept only ten orders per minute, the restaurant remains limited at the ordering stage even if the kitchen can prepare twenty dishes simultaneously.
A “wider front end” means that the CPU can fetch and decode more instructions per clock cycle, feeding its back-end execution units more effectively. The M5 widens the front end so that multiple back-end execution pipelines can remain more fully utilized. This is also an important source of its IPC improvement.
3. The Memory System: Unified Memory Architecture and Memory Bandwidth
3.1 Unified Memory Architecture (UMA)
In a traditional PC architecture, the CPU and GPU each have separate memory. The CPU uses DDR system memory, while the GPU uses its own VRAM. When the GPU needs data prepared by the CPU, that data must first be copied from system memory into VRAM, adding latency and imposing bandwidth limits.
Apple Silicon differs in that the CPU, GPU, and Neural Engine share one memory pool. The data remains in one place, and each processor reads it directly without a copy.
As you know from studying Transformers, model weights may need to be accessed by the GPU for matrix multiplication and by the Neural Engine for certain accelerated operations. Under a unified-memory architecture, the weights need to exist only once in memory and can be accessed directly by the CPU, GPU, and Neural Engine, eliminating data-transfer overhead.
This is also why the experience of 16 GB on an Apple device can approach that of 24–32 GB on a Windows laptop. In a traditional architecture, system memory and VRAM are allocated separately—for example, 16 GB of system memory plus 8 GB of VRAM. Apple’s 16 GB is shared by the CPU and GPU and can therefore be utilized more efficiently.
3.2 Memory Bandwidth
Memory bandwidth measures how much data can be read from or written to memory each second, in GB/s. The M4 provides 120 GB/s, while the M5 increases this to 153.6 GB/s.
LLM inference has two stages: prefill, which processes the entire input prompt, and decode, which generates one token at a time. The decode stage is primarily bottlenecked by memory bandwidth, because generating each token requires reading the entire set of model weights from memory.
For a concrete example, suppose a 7-billion-parameter model stored with 4-bit quantization occupies approximately 3.5 GB. Generating each token theoretically requires reading those 3.5 GB of weights. At 120 GB/s, one read takes about 29 ms; at 153.6 GB/s, it takes only about 23 ms. This directly determines how many tokens per second a local LLM can generate.
3.3 LPDDR5X
LPDDR5X is the specific memory standard. LPDDR means “Low Power Double Data Rate,” an energy-efficient memory standard commonly used in phones and laptops. 5X is an enhanced version of the fifth generation.
The M5 uses LPDDR5X-9600, where 9600 means 9,600 MT/s, or million transfers per second. Bandwidth is calculated as transfer rate × total bus width ÷ 8. The M5’s 153.6 GB/s figure follows from that specification and its bus width. You do not need to memorize the formula; the important point is that a higher number means faster data movement.
4. GPU and AI Acceleration: Neural Accelerators and Tensor Cores
This section relates directly to AI application engineering.
4.1 Matrix Multiplication
The central Self-Attention operation in a Transformer computes Q × K^T to obtain attention scores, then multiplies by V to produce the output. These are matrix multiplications. The entire Transformer—both its Attention and FFN layers—ultimately consists largely of matrix multiplication followed by activation functions.
GPUs are better suited than CPUs to this work because matrix multiplication can be parallelized extensively. A matrix contains thousands of elements, and each element can be computed independently. A GPU has hundreds or thousands of small cores that process many elements simultaneously. This is the fundamental reason GPUs outperform CPUs for AI workloads.
4.2 Tensor Cores / Neural Accelerators
A standard GPU core, or shader core, is general-purpose: it can perform any floating-point computation, including graphics rendering and general computation. For the operation most common in AI models—matrix multiplication, also called a tensor operation—a standard GPU core is not the most efficient hardware.
NVIDIA first added Tensor Cores to its GPUs as dedicated matrix-multiplication units. A Tensor Core can complete a small matrix multiplication, such as a 4 × 4 operation, in one clock cycle, while ordinary GPU cores need multiple cycles to perform the same work.
Apple has done something similar in the M5 under the name “Neural Accelerator.” Each M5 GPU core contains a Neural Accelerator dedicated to accelerating matrix multiplication.
In an analogy, an ordinary GPU core is a versatile worker who can perform any task but is only moderately efficient at each one. A Neural Accelerator is a matrix-operation specialist who does only one kind of work but performs it extremely efficiently. Embedding one in every GPU core is like assigning a specialist assistant to every general-purpose worker.
This is why the M5’s AI GPU compute performance is more than four times the M4’s: neither GPU core count nor frequency increased fourfold. Instead, dedicated matrix-multiplication hardware was added inside each core.
4.3 LLM Inference
Machine learning has two stages: training and inference. Training teaches a model; inference runs a trained model. When you run an LLM locally on a MacBook and converse with it, that process is inference.
Inference itself has two steps, as mentioned earlier:
Prefill: The model processes the entire input prompt at once. This stage is compute-bound, with GPU compute as the bottleneck. Neural Accelerators have a major effect here because the stage performs large numbers of matrix multiplications.
Decode: The model generates output tokens one by one. Generating each token requires reading all model weights. This stage is memory-bandwidth-bound, with memory bandwidth as the bottleneck. The M5’s 153.6 GB/s bandwidth therefore provides a direct benefit in this stage.
4.4 Diffusion Models
Diffusion models are another class of AI model, primarily used for image generation, including the underlying architecture of systems such as Stable Diffusion and DALL-E.
In simple terms, training repeatedly adds noise to a normal image until it becomes pure noise, then trains a neural network to denoise it and gradually reconstruct a clear image. During generation, the process begins with random noise and progressively denoises it until an image emerges.
Diffusion inference executes dozens of denoising steps, each involving large numbers of matrix operations. GPU performance, especially acceleration from Neural Accelerators, therefore has a substantial effect on generation speed.
4.5 GPU Quantized Score
This is a metric in the Geekbench AI benchmark. In this context, quantization compresses AI model weights from high-precision floating-point values such as FP32 to lower-precision formats such as INT8 or INT4.
A quantized model is smaller and faster, although it can theoretically lose some accuracy. In practical local LLM inference, almost everyone uses quantized models. A model run through llama.cpp on a Mac, for example, is commonly quantized to Q4 or Q5. The quantized score therefore reflects real-world experience better than a full-precision score.
The M5’s GPU quantized score is approximately 23,628, compared with about 11,616 for the M4. This near doubling directly corresponds to the speed difference when running quantized LLMs locally.
5. Chip Manufacturing and Packaging
5.1 The 3-Nanometer Process
The process node refers to the minimum dimensions of transistors on a chip. Three nanometers means that a transistor’s critical dimension is approximately 3 nm, where one nanometer is one-billionth of a meter. A smaller process can place more transistors on the same silicon area, making a chip more powerful, more energy-efficient, or both.
In practice, modern “3 nm” is more a commercial name than a strict physical measurement. The underlying logic remains valid: a more advanced process means higher transistor density and better performance per watt.
Both M4 and M5 use TSMC’s 3 nm process, but the M5 uses a third-generation 3 nm process—N3P or a similar improved version. It is optimized within the same nominal “3 nm” class to permit a higher frequency or lower leakage current.
5.2 Fusion Architecture: Dual-Die Packaging
Fusion Architecture is a new design introduced with the M5 Pro and M5 Max and is useful for understanding modern chip-design trends.
A die is a physical piece of silicon. Traditionally, one SoC, or system on a chip, consists of one die integrating the CPU, GPU, memory controller, and other components.
As chips grow larger, a single die encounters yield problems. Any defect on the silicon can render the entire chip unusable. A larger die is more likely to encounter a defect, lowering yield and increasing cost.
Fusion Architecture divides the chip into two smaller dies. They are manufactured separately, improving yield, and then joined through advanced packaging. High-bandwidth, low-latency interconnects let them operate like one chip. Intel calls its related technology Foveros, AMD uses 3D V-Cache and chiplet designs, and Apple now calls its approach Fusion Architecture.
The underlying idea is the same: combine several small chips to obtain the performance of one large chip while keeping yield and cost under control. M5 Pro and M5 Max use two 3 nm dies, allowing them to include 18 CPU cores and as many as 40 GPU cores.
6. Connectivity Terms
6.1 Wi-Fi 7 and Bluetooth 6
Wi-Fi 7, or 802.11be, is the latest Wi-Fi standard. Its theoretical maximum speed exceeds 40 Gbps, and it supports 320 MHz channels and Multi-Link Operation (MLO). The most practical benefit is that Wi-Fi 7’s lower latency and interference resistance should be noticeably better than Wi-Fi 6E in a crowded apartment-complex wireless environment.
Bluetooth 6 improves range, speed, and power efficiency, helping connection stability for devices such as AirPods.
These capabilities are implemented through Apple’s new N1 wireless chip. This is Apple’s first use of a separate chip to manage wireless connectivity, moving that function out of the main SoC to improve radio-frequency performance.
7. Connecting the Concepts: What Happens in Hardware During One LLM Inference
Consider a concrete scenario that connects all these concepts. Suppose you use the MLX framework to run a quantized 7B LLM locally on an M5 MacBook and enter a prompt.
Step 1: The tokenizer splits the prompt into tokens. The CPU performs this step, using its higher IPC and clock speed to complete it quickly.
Step 2 — Prefill: The token embeddings for the entire prompt pass through every model layer. The Attention and FFN operations in each layer are primarily matrix multiplications. The GPU takes over: ten GPU cores work in parallel, and the Neural Accelerator in each core specifically accelerates matrix multiplication. Model weights are loaded from unified LPDDR5X memory, with 153.6 GB/s of bandwidth, into caches close to the GPU cores. The unified-memory architecture eliminates a CPU-to-GPU copy.
Step 3 — Decode: The model begins generating a response token by token. Each generated token requires the model weights to be read again. A KV cache avoids recomputing the K and V values for previous tokens, but the weights themselves must still be read each time. Memory bandwidth is now the bottleneck: 153.6 GB/s determines how many tokens can be generated per second. The larger 28 MB L2 cache also helps because frequently used weight blocks can remain cached, reducing main-memory access.
Step 4: The CPU receives the generated tokens, decodes them back into text, and displays them on the screen.
Across this process, CPU IPC and clock speed affect steps 1 and 4, the GPU’s Neural Accelerators determine the speed of step 2, and memory bandwidth and cache determine the speed of step 3. Judging the system only by clock speed, or claiming that GPU improvements do not matter, is therefore highly one-sided.